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RT8113 1 ds8113-02 april 2011 www.richtek.com ordering information note : richtek products are : ` rohs compliant and compatible with the current require- ments of ipc/jedec j-std-020. ` suitable for use in snpb or pb-free soldering processes. single phase vr11.1 pwm controller with 7-bit vid applications atom v core power ibexpeak graphic power low voltage, high current dc/dc converter pin configurations (top view) wqfn-24l 4x4 general description the RT8113 is a single-phase pwm buck controller with one integrated mosfet driver for advanced microprocessor applications such as atom v core or ibexpeak graphic power. this controller maintains the same features as the multi-phase product family. however, it reduces the output to one phase for lower current systems. features of this controller include adjustable operation frequency, power good indication, external error amplifer compensation, over voltage protection, over current protection, droop enable/disable capability, externally adjustable offset voltage, load transient enhancement (quick response), and enable/shutdown pin to achieve optimal power management solution for various applications. the RT8113 comes in a wqfn-24l 4x4 package. features single-phase power conversion one embedded mosfet driver with internal bootstrap diode vid table for intel vr11.1 continuous differential inductor dcr current sense droop enable/disable capability adjustable soft-start adjustable frequency typically at 200khz power good indication adjustable over current protection over voltage protection over temperature protection small 24-lead wqfn package rohs compliant and halogen free marking information vid1 ocset fbrtn ss comp fb isn adj ofs rt/en isp vcc5 pgood boot phase vcc12 lgate ugate vid5 vid7 vid2 vid3 vid4 vid6 gnd 1 2 3 4 5 6 78910 12 11 18 17 16 15 14 13 21 20 19 24 22 23 25 dz= : product code ymdnn : date code dz=ym dnn package type qw : wqfn-24l 4x4 (w-type) lead plating system g : green (halogen free and pb free) RT8113
RT8113 2 ds8113-02 april 2011 www.richtek.com function block diagram typical application circuit v o u t 1 6 1 5 1 3 1 2 8 a d j r t / e n u g a t e i s n r t 8 1 1 3 l g a t e 7 9 1 7 b o o t o f s p h a s e f b i s p 1 1 1 2 v r 4 c 3 c 1 q 1 q 2 r 1 r 2 1 2 v s s 4 c 1 4 c o m p 5 f b r t n 3 6 g n d exposed pad (25) load e n o p t i o n f o r d i s a b l e d r o p v c c 1 2 1 4 v c c 5 1 0 1 9 , 2 0 , 2 1 , 2 2 , 2 3 , 2 4 , 1 v i d [ 7 : 1 ] c 1 1 c 9 c 1 0 c 5 c 6 c 7 c 8 c 1 2 c 1 3 r 2 0 r 1 9 r 1 3 r 5 r 6 r 9 r 1 0 r 1 2 n t c 1 8 p g o o d l 1 c 2 r 3 r 1 1 v c c _ s n s v s s _ s n s r r t q 3 2 o c s e t r 1 6 r 1 5 r 1 8 r 1 4 o p t i o n f o r n e g a t i v e o f s o p t i o n f o r p o s i t i v e o f s p g o o d r 1 7 v t t r 7 r 8 d 1 o p t i o n vid [7:1] + - cmp + - oc current sense /10 + - + - ov 150mv + transient response enhancement offset vr11 vid table soft start and fault logic vid off eap oc ov control mosfet driver power on reset 5v regulator modulation waveform generator por vcc12 fb comp fbrtn ss ugate phase ocset vcc12 ofs rt/en isp boot adj lgate isn vcc5 pgood + - ea gnd mosfet driver driver logic fault logic pwm thermal protection ot
RT8113 3 ds8113-02 april 2011 www.richtek.com pin no. pin name pin function 2 ocset over current protection threshold set pin. 3 fbrtn return ground. this pin is negative node of the differential remote voltage sending. 4 ss soft-start ramp slope set pin. connect this pin to fbrtn by a capacitor to adjust soft-start slew rate. 5 comp compensation pin. output of error amplifier and input of pwm comparator. 6 fb inverting input of error amplifier. 7 adj droop set pin. connect a resistor from this pin to gnd sets the load line slope. 8 ofs voltage offset pin. this pin sets no-load output voltage offset. connect a resistor from this pin to vcc5 or gnd to bidirection set the output voltage no-load offset. 9 rt/en switching frequency set pin. connect this pin to gnd via a resistor to adjust switching frequency and operate with droop function. connect this pin to vcc5 via a resistor to adjust switching frequency and operate without droop function. 10 vcc5 internal 5v regulator output. 11 isp non-invertering input of current sense amplifier. 12 isn invertering input of current sense amplifier. 13 lgate lower gate driver. this pin drives the gate of low side mosfets. 14 vcc12 12v power supply input pin. 15 phase switch node of high side driver. connect this pin to high-side mosfets sources together with the low side mosfets drains and inductor. 16 ugate upper gate driver. this pin drives the gate of the high-side mosfets. 17 boot bootstrap power pin. this pin powers the high-side mosfets drivers. connect this pin to the junction of the bootstrap capacitor with the cathode of the bootstrap diode. 18 pgood power good indicator. 19 to 24,1 vid7 to vid1 dac voltage identification inputs. 25 (exposed pad) gnd ground pin. the exposed pad must be soldered to a large pcb and connected to agnd for maximum power dissipation. functional pin description
RT8113 4 ds8113-02 april 2011 www.richtek.com table 1. output voltage program to be continued pin name vid7 vid6 vid5 vid4 vid3 vid2 vid1 nominal output voltage dacout 0 0 0 0 0 0 0 off 0 0 0 0 0 0 1 1.60000v 0 0 0 0 0 1 0 1.58750v 0 0 0 0 0 1 1 1.57500v 0 0 0 0 1 0 0 1.56250v 0 0 0 0 1 0 1 1.55000v 0 0 0 0 1 1 0 1.53750v 0 0 0 0 1 1 1 1.52500v 0 0 0 1 0 0 0 1.51250v 0 0 0 1 0 0 1 1.50000v 0 0 0 1 0 1 0 1.48750v 0 0 0 1 0 1 1 1.47500v 0 0 0 1 1 0 0 1.46250v 0 0 0 1 1 0 1 1.45000v 0 0 0 1 1 1 0 1.43750v 0 0 0 1 1 1 1 1.42500v 0 0 1 0 0 0 0 1.41250v 0 0 1 0 0 0 1 1.40000v 0 0 1 0 0 1 0 1.38750v 0 0 1 0 0 1 1 1.37500v 0 0 1 0 1 0 0 1.36250v 0 0 1 0 1 0 1 1.35000v 0 0 1 0 1 1 0 1.33750v 0 0 1 0 1 1 1 1.32500v 0 0 1 1 0 0 0 1.31250v 0 0 1 1 0 0 1 1.30000v 0 0 1 1 0 1 0 1.28750v 0 0 1 1 0 1 1 1.27500v 0 0 1 1 1 0 0 1.26250v 0 0 1 1 1 0 1 1.25000v 0 0 1 1 1 1 0 1.23750v 0 0 1 1 1 1 1 1.22500v 0 1 0 0 0 0 0 1.21250v 0 1 0 0 0 0 1 1.20000v 0 1 0 0 0 1 0 1.18750v 0 1 0 0 0 1 1 1.17500v 0 1 0 0 1 0 0 1.16250v 0 1 0 0 1 0 1 1.15000v 0 1 0 0 1 1 0 1.13750v 0 1 0 0 1 1 1 1.12500v
RT8113 5 ds8113-02 april 2011 www.richtek.com to be continued table 1. output voltage program pin name vid7 vid6 vid5 vid4 vid3 vid2 vid1 nominal output voltage dacout 0 1 0 1 0 0 0 1.11250v 0 1 0 1 0 0 1 1.10000v 0 1 0 1 0 1 0 1.08750v 0 1 0 1 0 1 1 1.07500v 0 1 0 1 1 0 0 1.06250v 0 1 0 1 1 0 1 1.05000v 0 1 0 1 1 1 0 1.03750v 0 1 0 1 1 1 1 1.02500v 0 1 1 0 0 0 0 1.01250v 0 1 1 0 0 0 1 1.00000v 0 1 1 0 0 1 0 0.98750v 0 1 1 0 0 1 1 0.97500v 0 1 1 0 1 0 0 0.96250v 0 1 1 0 1 0 1 0.95000v 0 1 1 0 1 1 0 0.93750v 0 1 1 0 1 1 1 0.92500v 0 1 1 1 0 0 0 0.91250v 0 1 1 1 0 0 1 0.90000v 0 1 1 1 0 1 0 0.88750v 0 1 1 1 0 1 1 0.87500v 0 1 1 1 1 0 0 0.86250v 0 1 1 1 1 0 1 0.85000v 0 1 1 1 1 1 0 0.83750v 0 1 1 1 1 1 1 0.82500v 1 0 0 0 0 0 0 0.81250v 1 0 0 0 0 0 1 0.80000v 1 0 0 0 0 1 0 0.78750v 1 0 0 0 0 1 1 0.77500v 1 0 0 0 1 0 0 0.76250v 1 0 0 0 1 0 1 0.75000v 1 0 0 0 1 1 0 0.73750v 1 0 0 0 1 1 1 0.72500v 1 0 0 1 0 0 0 0.71250v 1 0 0 1 0 0 1 0.70000v 1 0 0 1 0 1 0 0.68750v 1 0 0 1 0 1 1 0.67500v 1 0 0 1 1 0 0 0.66250v 1 0 0 1 1 0 1 0.65000v 1 0 0 1 1 1 0 0.63750v 1 0 0 1 1 1 1 0.62500v
RT8113 6 ds8113-02 april 2011 www.richtek.com table 1. output voltage program pin name vid7 vid6 vid5 vid4 vid3 vid2 vid1 nominal output voltage dacout 1 0 1 0 0 0 0 0.61250v 1 0 1 0 0 0 1 0.60000v 1 0 1 0 0 1 0 0.58750v 1 0 1 0 0 1 1 0.57500v 1 0 1 0 1 0 0 0.56250v 1 0 1 0 1 0 1 0.55000v 1 0 1 0 1 1 0 0.53750v 1 0 1 0 1 1 1 0.52500v 1 0 1 1 0 0 0 0.51250v 1 0 1 1 0 0 1 0.50000v 1 1 1 1 1 1 1 off
RT8113 7 ds8113-02 april 2011 www.richtek.com parameter symbol test conditions min typ max unit vcc12 supply input vcc12 supply current i cc -- 6 -- ma vcc5 power vcc5 output voltage v cc5 i load = 10ma 4.9 5 5.1 v vcc5 output sourcing i vcc 5 10 -- -- ma power-on reset vcc12 rising threshold v cc12_th vcc12 rising 9.2 9.7 10.2 v vcc12 hysteresis v cc12_hy vcc12 falling -- 0.9 -- v vcc5 rising threshold v cc5_th vcc5 rising 4.4 4.6 4.8 v vcc5 hysteresis v cc5_hy vcc5 falling -- 0.4 -- v (t a = 25 c, unless otherwise specified) electrical characteristics recommended operating conditions (note 4) supply input voltage, vcc12 ----------------------------------------------------------------------- 12v 10% junction temperature range ------------------------------------------------------------------------- ? 40 c to 125 c ambient temperature range ------------------------------------------------------------------------- ? 40 c to 85 c absolute maximum ratings (note 1) supply input voltage, vcc12 --------------------------------------------------------------------- ? 0.3v to 15v bootx to gnd dc -------------------------------------------------------------------------------------------------------- ? 0.3v to 30v < 200ns ------------------------------------------------------------------------------------------------- ? 0.3v to 42v phasex to gnd dc -------------------------------------------------------------------------------------------------------- ? 2v to 15v < 200ns ------------------------------------------------------------------------------------------------- ? 5v to 30v ugatex to gnd -------------------------------------------------------------------------------------- (v phase ? 0.3v) to (v boot + 0.3v) < 200ns ------------------------------------------------------------------------------------------------- (v phase ? 5v) to (v boot + 5v) lgatex to gnd -------------------------------------------------------------------------------------- (gnd ? 0.3v) to (v cc + 0.3v) < 200ns ------------------------------------------------------------------------------------------------- (gnd ? 5v) to (v cc + 5v) other pins ---------------------------------------------------------------------------------------------- ? 0.3v to 6.5v power dissipation, p d @ t a = 25 c wqf n-24l 4x4 --------------------------------------------------------------------------------------- 1.923w package thermal resistance (note 2) wqfn-24l 4x4, ja ---------------------------------------------------------------------------------- 52 c/w wqfn-24l 4x4, jc --------------------------------------------------------------------------------- 7 c/w lead temperature (soldering, 10 sec.) ---------------------------------------------------------- 260 c junction temperature -------------------------------------------------------------------------------- 150 c storage temperature range ----------------------- ------------------------------------------------ ? 65 c to 150 c esd susceptibility (note 3) hbm (human body mode) -------------------- ----------------------------------------------------- 2kv mm (ma chine mode) --------------------------------------------------------------------------------- 200v to be continued to be continued
RT8113 8 ds8113-02 april 2011 www.richtek.com to be continued parameter symbol test conditions min typ max unit rt/en chip disable threshold v dis -- -- 0.4 v running frequency f osc r rt = 60k 180 200 220 khz rt pin voltage v rt, gnd r rt = 60k , connected between rt/en and gnd 1.52 1.6 1.68 v rt pin voltage v rt, vdd r rt = 60k , connected between rt/en and v cc5 v cc5 ? 1.68 v cc5 ? 1.6 v cc5 ? 1.52 v modulation gain a ramp r rt = 60k -- 22 -- %/v reference voltage accuracy 1v to 1.6v ? 0.5 -- 0.5 % 0.8v to 1v ? 5 -- 5 mv dac accuracy 0.5v to 0.8v ? 8 -- 8 mv logic-low v il vid [7:1] -- -- 0.4 v vid threshold vo lta ge logic-high v ih vid [7:1] 0.8 -- -- v error amplifier dc gain a dc no load -- 80 -- db gain-bandwidth gbw c load = 10pf -- 10 -- mhz slew rate sr c load = 10pf 10 -- -- v/ s output voltage range v comp 0.5 -- 3.6 v maximum current i ea_slew slew 300 -- -- a power sequence pgood low voltage v pgood i pgood = 4ma -- -- 0.4 v soft-start delay t d1 after por, from en = high to v out rising 0 -- 5 ms v boot duration t d3 0.05 -- 3 ms pgood delay t d5 measured from final v out value to pgood = high 0.05 -- 3 ms current sense amplifier maximum current i gmmax v csp = 1.3v, sink current from csn 100 -- -- a input offset voltage v oscs ? 1.5 0 1.5 mv soft start soft start current i ss1 slew 12 16 20 a vid change current i ss2 slew 120 160 200 a gate driver ugate drive source i ug atesr boot ? phase = 12v, ugate ? phase = 6v 0.6 1 -- a ugate drive sink r ugatesk boot ? phase = 8v, 250ma source current -- 1 -- lgate drive source i lg atesr v cc12 = 12v, v lgate = 6v 0.6 1 -- a lgate drive sink r lgatesk 250ma sink current -- 0.8 -- protection over-voltage threshold v ovp sweep fb voltage, v fb ? v eap 125 150 175 mv ocp input offset voltage v ocofs ? 10 -- 10 mv
RT8113 9 ds8113-02 april 2011 www.richtek.com note 1. stresses listed as the above ? absolute maximum ratings ? may cause permanent damage to the device. these are for stress ratings. functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. note 2. ja is measured in natural convection at t a = 25 c on a high effective thermal conductivity four-layer test board of jedec 51-7 thermal measurement standard. the measurement case position of jc is on the exposed pad of the package. note 3. devices are esd sensitive. handling precaution is recommended. note 4. the device is not guaranteed to function outside its operating conditions. parameter symbol test conditions min typ max unit over temperature shutdown setpoint t sd -- 160 -- c dynamic characteristic ugate rise time t rugate - 15 - ns ugate fall time t fugate - 10 - ns lgate rise time t rlgate - 15 - ns lgate rise time t flgate c iss = 3000pf - 10 - ns
RT8113 10 ds8113-02 april 2011 www.richtek.com typical operating characteristics vid = 0.9v, i load = 1a power off from rt/en time (400 s/div) pgood (2v/div) v out (1v/div) rt/en (2v/div) ugate (20v/div) vid = 0.9v, i load = 1a start up from rt/en time (1ms/div) pgood (2v/div) v out (1v/div) rt/en (2v/div) ugate (20v/div) vid from 0.675v up to 1.3v, i load = 16a dynamic vid up time (40 s/div) v out (500mv/div) vid1 (1v/div) vid from 1.3v down to 0.675v, i load = 16a dynamic vid down time (40 s/div) v out (500mv/div) vid1 (1v/div) load transient response time (10 s/div) i load v out (20mv/div) vid = 1.3v, f load = 1khz, i load = 7a to 20a -> 1.2v 7a 20a load transient response time (10 s/div) i load v out (20mv/div) vid = 1.3v, f load = 1khz, i load = 20a to 7a -> 1.2v 7a 20a
RT8113 11 ds8113-02 april 2011 www.richtek.com over current protection time (200 s/div) pgood (5v/div) v out (1v/div) ugate (50v/div) i load (50a/div) over voltage protection time (20 s/div) pgood (5v/div) v fb (1v/div) ugate (20v/div) lgate (10v/div)
RT8113 12 ds8113-02 april 2011 www.richtek.com applications information the RT8113 is a single-phase synchronous buck dc/dc converter with embedded mosfet driver. the internal vid dac is designed to interface with the intel 7-bit vr11.x compatible vid table for ibexpeak platf orm cpu?s axg vr application. supply voltage, vcc5 regulation and por there are two supply voltage pins built-in in the RT8113, vcc12 and vcc5. vcc12 is a power input pin which receives external 12v voltage for embedded driver logic operation. vcc5 is a power output pin which is the output of an internal 5v ldo regulator. the mentioned 5v ldo regulator regulates vcc12 to generate a 5v voltage source for internal gate logic and external circuit biasing, e.g., ocp biasing. since the vcc5 voltage is regulated, the variation of vcc5 (2%) will be much smaller than platform atx +5v (5%~7%). the maximum supply current of vcc5 is 10ma, which is designed only for controller circuit biasing. the recommended configuration of the RT8113 supply voltages is as follows: platform atx +12v to the vcc12 pin, and decoupling capacitors on the vcc12 and vcc5 pins (minimum 0.1 f). the initialization of the RT8113 requires both the voltage on the vcc12 and vcc5 to be ready. since vcc5 is regulated internally from vcc12, the vcc5 voltage will be ready (>4.6v) after vcc12 reaches about 7v, so there is no power sequence problem between vcc12 and vcc5. after vcc5 > 4.6v and vcc12 > 9.6v, the internal power-on-reset (por) signal goes high. this por signal indicates the power supply voltages are all ready and initiates soft-start sequence. when por = low, the RT8113 will try to turn off both high-side and low-side mosfets to prevent catastrophic failure. + - cmp + - cmp 4.6v 9.6v vcc12 vcc5 por por : power on reset figure 1. circuit for power ready detection switching frequency the switching frequency of the RT8113 is set by an external resistor connected from the rt/en pin either to gnd or to vcc5. if the resistor is connected from rt/en to gnd, the load line function will be enabled as well. more details will be described in the load line section. the frequency follows the graph in figure 2. figure 2. switching frequency vs. r rt resistance chip enable the enable function of the RT8113 is combined in the rt/en pin. besides frequency setting function, pulling the rt/en pin to gnd can also force the RT8113 to enter soft shutdown sequence. it is recommended to connect a control switch from the rt/en pin to gnd in parallel with rt setting resistors. the RT8113 will enter soft shutdown sequence when the control switch is turned on. soft-start the v out soft-start slew rate is set by a capacitor from the ss pin to fbrtn. before power on reset (por = low), the ss pin is held at gnd. after power on reset (por = high) and an extra delay of 1600 s (t d1 ), the controller initiates ramping up. v out will always trace v eap during normal operation of the RT8113, where v eap is the positive input of compensation error amplifier, which can be described as v eap = v dac ? v adj (the definition of v adj will be described later in the load line section). the first ramping up duration of v out (t d2 ) ramps v out to v boot . 0 200 400 600 800 1000 0 1020304050607080 r rt switching frequency (khz) 1 (k )
RT8113 13 ds8113-02 april 2011 www.richtek.com after v out ramps to v boot , the RT8113 stays in this state for 800 s (t d3 ) waiting for valid vid code sent by cpu. after receiving valid vid code, v out continues ramping up or down to the voltage specified by vid code. after v out ramps to v eap = v dac ? v adj , the RT8113 stays in this state for 1600 s (t d5 ) and then asserts pgood = high. the ramping slew rate of t d2 and t d4 is controlled by the external capacitor connected to ss pin. the voltage of figure 3 . circuit for soft-start and dynamic vid figure 4. soft-start wave forms soft start circuit v dac i ss eap (error amp positive input) soft start current (i ss ) is limited and variant r2 r1 r3 c2 c1 c3 v out fb comp adj ss c ss r adj + - ea vcc12 vcc5 9.6v 4.6v v dac ss pgood t d1 v out v boot t d2 t d3 t d4 t d5 the ss pin will always be v eap +0.7v, where the mentioned 0.7v is the typical turn-on threshold of an internal power switch. before pgood = high, the slew rate of v eap is limited to 16 a/c ss . when pgood = high, the slew rate of v eap is limited to 160 a/c ss , which is 10 times faster than soft start slew rate for dynamic vid feature. the soft start waveform is shown in figure 4.
RT8113 14 ds8113-02 april 2011 www.richtek.com dynamic vid the RT8113 can accept vid input changing while the controller is running. this allows the output voltage (v out ) to change while the dc/dc converter is running and supplying current to the load. this is commonly referred to as vid on-the-fly (otf). a vid otf can occur under either light or heavy load conditions. the cpu changes the vid inputs in multiple steps from the start code to the finish code. this change can be positive or negative. theoretically, v out should follow v dac , which is a staircase waveform, but in real application, the bandwidth of the converter is finite while the staircase waveform needs infinite bandwidth to follow. thus, undesired v out overshoot (when v dac changes up) or undershoot (when v dac changes down) is often observed in these type of designs. however, for the RT8113, as mentioned before in the soft-start section, v dac slew rate is limited by i ss2 /c ss when pgood = high. this slew rate limiter works as a low-pass filter of v dac and makes the bandwidth of v dac waveform finite. by smoothening v dac staircase waveform, v out will no longer overshoot or undershoot. on the other hand, c ss will increase the settling time of v out during vid otf. in most cases, a 1nf to 30nf ceramic capacitor will be suitable for c ss . fb ofsn ofsn fb ofs 0.8 x r v = i x r = r connect a resistor from the ofs pin to vcc5 to activate i ofsp . i ofsp flows through r fb from the v ccp to the fb pin. in this case, a positive no-load offset voltage (v ofsp ) is generated. fb ofsp ofsp fb ofs 6.4 x r v = i x r = r d1 out ss d1 d2 out out boot boot ss d2 d3 t is the delay time from power on reset state to the beginning of v rising. 0.7v x c t = 1600 s + 16 a t is the soft-start time from v = 0 to v = v . v x c t = 16 a t is the out boot d3 d4 out boot out dac dac boot d4 d5 d5 dwelling time for v = v . t 800 s. t is the soft-start time from v = v to v = v . v - v x css t 16 a t is the power good delay time. t1600 s. ? ? ? output voltage differential sensing the RT8113 uses a high-gain low-offset error amplifier for differential sensing. the cpu voltage is sensed between the fb and fbrtn pins. a resistor (r fb ) connects the fb pin with the positive remote sense pin of the cpu (v ccp ), while the fbrtn pin connects directly to the negative remote sense pin of the cpu (v ccn ). the error amplifier compares v eap (= v dac ? v adj ) with the v fb to regulate the output voltage. no-load offset in figure 5, i ofsn and i ofsp are used to generate no-load offset. either i ofsn or i ofsp is active during normal operation. connect a resistor from ofs pin to gnd to activate i ofsn . i ofsn flows through r fb from the fb pin to v ccp . in this case, a negative no-load offset voltage (v ofsn ) is generated.
RT8113 15 ds8113-02 april 2011 www.richtek.com figure 5. circuit for v out differential sensing and no load offset load transient quick response in steady state, the voltage of v fb is controlled to be very close to v eap . however while a load step transient from light load to heavy load could cause v fb to be lower than v eap by several tens of mv. in conventional buck converter design (without non-linear control) for cpu vr application, due to limited control bandwidth, it is hard for the vr to prevent v out undershoot during quick load transient from light load to heavy load. hence, the RT8113 builds in a state-of-the-art quick response function which detects load figure 6. load transient quick response v eap = v dac - v adj v out fb comp r fb c fb r1 c1 c2 qr circuit i out v out qr + - ea c2 + - + v dac - eap comp fbrtn r adj adj i ofsp i ofsp r1 c1 c fb r fb (positive remote sense pin of cpu) v cc_sns v ss_sns (negative remote sense pin of cpu) fb + - transient by comparing v fb and v eap . if v fb suddenly drops below ? v eap ? v qr ? where v qr is a predetermined voltage (~40mv), the quick response indicator qr rises up. when qr = high, the RT8113 turns on all high side mosfets and turns off all low side mosfets. the sensitivity of quick response can be adjusted by varying the values of c fb and r fb . smaller r fb and/or larger c fb will make qr easier to be triggered. figure 6 is the circuit and typical waveforms.
RT8113 16 ds8113-02 april 2011 www.richtek.com output current sensing the RT8113 provides a low input offset current-sense amplifier (csa) to monitor the output current. the output current of csa (i x ) is used for load line control and over- current protection. in this inductor current sensing topology, r s and c s must be set according to the equation below : then the output current of csa will follow the equation below : ss l = r x c dcr ( ) l ofs-csa csp s csn x csn i x dcr - v + 700n x r + r - r i = r figure 7. circuit for current sensing l x csn i x dcr i = r r csn r csp l dcr r s c s isn isp csa: current sense amplifier r2 c2 c1 r1 v in lgate phase ugate boot 700na v ofs_csa 700na + - + - i x 700na is a typical value of the csa input offset current. v ofs-csa is the input offset voltage of csa. v ofs-csa of the RT8113 is smaller than +/- 1.5mv. usually, ? v ofs-csa + 700n x (r csp + r s - r csn ) ? is negligible except at very light load and the equation can be simplified as the equation below :
RT8113 17 ds8113-02 april 2011 www.richtek.com load line the RT8113 utilizes inductor dcr current sense technique for load line control function. the sensed inductor current i x is multiplied by 0.5 and sent to adj pin. after the current 0.5 x i x injects into the adj resistors, the voltage of the adj pin is established. the v adj is then multiplied by 0.1 and subtracted by v dac to generate v eap . because i x is a ptc (positive temperature coefficient) current, an ntc (negative temperature coefficient) resistor is needed to connect adj pin to gnd. if the ntc resistor is properly selected to compensate the temperature coefficient of i x , the voltage on adj pin will be proportional to i out without temperature effect. in the RT8113, the positive input of error amplifier is ? v dac ? 0.1 x v adj ? and v out will follow ? v dac ? 0.1 x v adj ? . thus, the output voltage which decreases linearly with i out is obtained. the load line is defined as : adj x adj out adj adj out out csn 1 v = x i x r 2 v v dcr x r 1 ll(load line) = = x = i10i 20 x r ? ? basically, the resistance of r adj sets the resistance of the load line. the temperature coefficient of r adj compensates the temperature effect of the load line. the load line function of the RT8113 can be disabled by connecting the rt/en pin resistor to vcc5 instead of gnd. when the rt/en pin resistor is connected to vcc5, the current-sense circuit works normally while v eap no longer contains droop, and the reference voltage of the error amplifier will remain equal to v dac regardless of output current. the running frequency of the RT8113 will always be the same whether connecting rt/en to vcc5 or gnd. over current protection (ocp) in figure 8, v ocset is equal to vcc x r2/(r1 + r2). for the RT8113, v adj is proportional to i out and is thermally compensated. once v adj is larger than v ocset , ocp is triggered and latched. the ocp function will not be influenced by enabling or disabling load line since the voltage on the adj pin always contains real-time information of load current. once ocp is triggered, the RT8113 will turn off both high-side mosfets and low side mosfets. vcc5 or vcc12 adj ocset ocp r1 r2 cmp + - figure 8. over current protection over voltage protection (ovp) the over-voltage protection monitors the output voltage via the fb pin. once v fb exceeds ? v eap + 150mv ? , ovp is triggered and latched. the RT8113 will turn on low-side mosfet and turn off high side mosfet to protect cpu. a 20 s delay is used in ovp detection circuit to prevent false trigger. over temperature protection (otp) the over-temperature protection function of the RT8113 is built inside the controller to prevent overheat damage. otp occurs when the die temperature of the RT8113 exceeds 160 c, in which the RT8113 then turns off both high-side mosfets and low side mosfets. loop compensation the RT8113 is a voltage mode controller and requires external compensation. to compensate a typical voltage mode buck converter, there are two ordinary compensation schemes, commonly known as type-ii compensator and type-iii compensator. the choice of using type-ii or type- iii compensator lies with the platform designers, and the main concern deals with the position of the capacitor esr zero and mid-frequency to high-frequency gain boost. typically, the esr zero of output capacitor will tend to stabilize the effect of output lc double poles. hence, the position of the output capacitor esr zero in frequency domain may influence the design of voltage loop compensation. figure 9 shows a typical control loop using type-iii compensator. below is the compensator design procedure.
RT8113 18 ds8113-02 april 2011 www.richtek.com figure 9. compensation circuit 1) modulator characteristic the modulator consists of the pwm comparator and power stage. the pwm comparator compares error amplifier ea output (comp) with oscillator (osc) sawtooth wave to provide a pulse-width modulated (pwm) gate-driving signal. the pwm wave is smoothed out by the output filter, l out and c out . the output voltage (v out ) is sensed and fed to the inverting input of the error amplifier. the modulator transfer function is the small-signal transfer function of v out /v comp (output voltage over the error amplifier output). this transfer function is dominated by a dc gain, a double pole, and an esr zero as shown in figure 10. the dc gain of the modulator is the input voltage (v in ) divided by the peak-to-peak oscillator voltage v osc . the output lc filter introduces a double pole, 40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 degrees. the resonant frequency of the lc filter is expressed as : lc out out 1 f = 2 x l x c the esr zero is contributed by the esr associated with the output capacitance. note that this requires the output capacitor to have enough esr to satisfy stability requirements. the esr zero of the output capacitor is expressed as the following equation : esr out 1 f = 2 x c x esr figure 10. bode plot of loop gain 2) design the compensator a well-designed compensator regulates the output voltage to the reference voltage v ref with fast transient response and good stability. in order to achieve fast transient response and accurate output regulation, an adequate compensator design is necessary. the goal of the compensation network is to provide adequate phase margin (usually greater than 45 c) and the highest bandwidth (0db crossing frequency, f c ) possible. it is also recommended to manipulate loop frequency response that its gain crosses over 0db at a slope of -20db/dec. according to figure 10, the location of poles and zeros are : () 1 z1 z2 p1 p2 p3 1 f = 2 x r2 x c1 1 f = 2 x r1 + r3 x c3 f = 0 1 f = 2 x c3 x r3 f = c1 x c2 x r2 2 x c1 + c2 generally, f z1 and f z2 are designed to cancel the double pole of modulation. usually, place f z1 at a fraction of the f p3 f p2 f z2 f z1 gain log log frequency 0 f lc f esr f c modulator gain compensation gain closed loop gain - + + - osc v osc z fb z in v in driver driver ref pwm comparator comp ea + - ref ea z fb z in v out fb comp c1 c2 c3 r1 r2 r3 esr c out v out l
RT8113 19 ds8113-02 april 2011 www.richtek.com f lc , and place f z2 at f lc . f p2 is usually placed at f esr to cancel the esr zero. and f p3 is placed below switching frequency to cancel high frequency noise. for given bandwith, r2, f z1 , f z2 , f p2 , f p3 , then z1 mod@bw c z2 p2 p3 1 c1 = 2 x f x r2 g c3 = 2 x f x r2 1 r1 = 2 x f x c3 1 r3 = 2 x f x c3 c1 c2 = 2 x f x c1 x r2 -1 thermal considerations for continuous operation, do not exceed absolute maximum junction temperature. the maximum power dissipation depends on the thermal resistance of ic package, pcb layout, rate of surrounding airflow and temperature difference between junction to ambient. the maximum power dissipation can be calculated by following the formula : p d(max) = (t j(max) ? t a ) / ja where t j(max) is the maximum junction temperature, t a is the ambient temperature and ja is the junction to ambient thermal resistance. for recommended operating conditions specification of the RT8113, the maximum junction temperature is 125 c and t a is the ambient temperature. the junction to ambient thermal resistance ja is layout dependent. for wqfn-24l 4x4 packages, the thermal resistance ja is 52 c/w on the standard jedec 51-7 four-layer thermal test board. the maximum power dissipation at t a = 25 c can be calculated by the following formula : p d(max) = (125 c ? 25 c) / (52 c/w) = 1.923w for wqfn-24l 4x4 package the maximum power dissipation depends on operating ambient temperature for fixed t j (max) and thermal resistance ja . for RT8113 package, the derating curve in figure 11 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. layout considerations for best performance of the RT8113, the following guidelines must be strictly followed : ` the power components should be placed first. keep the connection between power components as short as possible. ` the shape of the phase plane (the connection plane between high side mosfets, low-side mosfets and output inductors) has to be as square as possible. long traces, thin bars or separated islands must be avoided in the phase plane. ` keep snubber circuits or damping elements near its objects. phase rc snubbers have to be close to low- side mosfets, ugate damping resistor has to be close to high-side mosfets, and boot to phase damping resistor has to be close to high-side mosfets and phase plane. also, keep the traces of these snubber circuits as short as possible. ` the area of v in plane (power stage 12v v in ) and v out plane (output bulk capacitors and inductor connection plane) has to be as wide as possible. long traces or thin bars must be avoided in these planes. the plane trace width must be wide enough to carry large input/ output current (40mm/a). ` the following traces have to be wide and short : ugate, lgate, boot, phase, and vcc12. make sure the widths of these traces are wide enough to carry large driving current (at least 40mm). figure 11. derating curves for RT8113 package 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 0255075100125 ambient temperature (c) maximum power dissipation (w) 1 four-layer pcb
RT8113 20 ds8113-02 april 2011 www.richtek.com ` the voltage feedback loop contains two traces, vcc and vss, which are kelvin sensed from cpu socket or output capacitors. these two traces should have 10mm width and be placed away from high (di/dt) switching elements such as high-side mosfets, low-side mosfets, phase plane etc. the circuit elements of voltage feedback loop, such as feedback loop short resistors and voltage loop compensation rcs, have to be kept near the RT8113 and also away from switching elements. ` the current-sense mechanism of the RT8113 is fully differential kelvin sense. therefore, the current-sense loop of the RT8113 contain two traces : the positive trace(isp) comes from the positive node the of output inductor (the node connecting phase plane) and the negative trace (isn) comes from the negative node of the output inductor (the node connecting output plane). do not connect the current-sense traces from the phase plane or output plane. only connect these traces from both sides of the output inductor to achieve the goal of precise kelvin sense. the current-sense feedback loops have to be routed away from switching elements, and the current-sense rc elements have to be put near their respective isn or isp pins of the RT8113 and also away from noise switching elements. at lease 10 mm width is suggested for current sense feedback loops.
RT8113 21 ds8113-02 april 2011 www.richtek.com richtek technology corporation headquarter 5f, no. 20, taiyuen street, chupei city hsinchu, taiwan, r.o.c. tel: (8863)5526789 fax: (8863)5526611 information that is provided by richtek technology corporation is believed to be accurate and reliable. richtek reserves the ri ght to make any change in circuit design, specification or other related things if necessary without notice at any time. no third party intellectual property inf ringement of the applications should be guaranteed by users when integrating richtek products into any application. no legal responsibility for any said applications i s assumed by richtek. richtek technology corporation taipei office (marketing) 5f, no. 95, minchiuan road, hsintien city taipei county, taiwan, r.o.c. tel: (8862)86672399 fax: (8862)86672377 email: marketing@richtek.com outline dimension a a1 a3 d e d2 e2 l b e 1 see detail a dimensions in millimeters dimensions in inches symbol min max min max a 0.700 0.800 0.028 0.031 a1 0.000 0.050 0.000 0.002 a3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 d 3.950 4.050 0.156 0.159 d2 2.300 2.750 0.091 0.108 e 3.950 4.050 0.156 0.159 e2 2.300 2.750 0.091 0.108 e 0.500 0.020 l 0.350 0.450 0.014 0.018 w-type 24l qfn 4x4 package note : the configuration of the pin #1 identifier is optional, but must be located within the zone indicated. det ail a pin #1 id and tie bar mark options 1 1 2 2

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